Double-masking technique for increasing fabrication yield in superconducting electronics

ABSTRACT

An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. application Ser. No. 14/850,634, filed Sep. 10, 2015, now U.S. Pat. No. 9,595,656, issued Mar. 14, 2017, which is a Division of U.S. application Ser. No. 13/771,330, filed Feb. 20, 2013, now U.S. Pat. No. 9,136,457, issued Sep. 15, 2015, which is a Continuation of U.S. application Ser. No. 13/073,954, filed Mar. 28, 2011, issued Feb. 26, 2013 as U.S. Pat. No. 8,383,426, which is a Continuation of U.S. application Ser. No. 12/346,603, filed Dec. 30, 2008, which is a Continuation of 11/616,382, filed Dec. 27, 2006, now U.S. Pat. No. 7,615,385, each of which are expressly incorporated herein by reference. This application is related to and claims priority to U.S. Provisional Application 60/826,262 filed Sep. 20, 2006 by inventor Sergey K. Tolpygo entitled A Double-Masking Technique for Increasing Fabrication Yield and Josephson Junction Quality in Superconducting Electronics, the contents of which is incorporated herein by reference in its entirety.

STATEMENT OF GOVERNMENT RIGHTS

This invention was developed in part under contract number N0014-03-C-0370 from the Office of Naval Research. The government has certain rights in this invention.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention is directed to fabrication of electronic devices and more particularly to the fabrication of superconducting electronic devices such as Josephson junctions.

2. Description of the Prior Art

Superconducting integrated circuits (ICs) based on Josephson junctions offer the possibility of operation at clock frequencies of 100 GHz or above. In order to achieve this on an industrial scale, it is necessary to decrease junction size toward submicron dimensions, and increase junction density, so that chips with many thousands of Josephson junctions can be reliably manufactured. The key parameter is the critical current I_(c) of a junction, which must be defined to within about 1% of design specifications, without defects.

The most reliable junction fabrication technology is based on the superconductor niobium (Nb), and in particular on a trilayer structure based on an ultrathin insulating “tunnel barrier” layer of aluminum oxide (AlO_(x)), 1-2 nm thick, sandwiched between two layers of Nb. This provides a precise critical current density of the junction J_(c)=I_(c)/A, where A is the junction area. If the microlithography defines A accurately, without damaging the tunnel barrier layer, then I_(c) is also accurately defined. This becomes increasingly difficult as the dimensions of the junction decrease. Applications of standard microlithography techniques may produce junctions with edge damage that can reduce junction quality and yield.

Current Nb IC technology also incorporates multiple layers of superconducting Nb wiring to bias and connect the Josephson junctions. This requires high-quality insulating layers between Nb layers, which are typically provided by silicon dioxide (SiO₂). SiO₂ is of course a standard material in semiconductor technology, and standard procedures for fabricating high-quality films are available.

An established technique in the prior art to improve junction yield is the use of selective anodization (Meng 2003, Kerber 2006). Anodization is an electrolytic process of surface oxidation that passivates all exposed Nb and Al surfaces, preventing damage in subsequent lithographic steps. However, this has not completely eliminated defects and related yield problems. It is essential to solve these problems to advance to the next stage of circuit integration.

PROBLEMS OF THE PRIOR ART

As indicated above, the techniques of the prior art have resulted in a number of problems. Specifically, the techniques of the prior art have resulted in low yield, that is, a large number of junctions fabricated on a silicon based wafer fail for a variety of reasons. This results in a substantial percentage of defective junctions on each wafer.

Sometimes part of a junction will simply peel off the wafer upon which it is fabricated, due in part to local stresses that result from the anodization procedure. Further, the prior art does not allow precise control of critical current densities of a junction. Yet another problem stems from the fact that the standard process includes a wet-etching step to remove the anodized AlOx layer, which also limits device yield.

SUMMARY OF THE INVENTION

Maintaining ideal adhesion between layers is essential for microlithographic control, and is especially critical during the selective anodization step of junction definition. During this step, penetration of the anodization solution (the electrolyte) under the resist would cause major fabrication defects. Standard resists have been optimized for the semiconductor industry, where the most critical materials are Si and SiO₂, and adhesion of resists to these materials is outstanding. In contrast, no such optimization exists for Nb, the key material for superconducting circuits. In the present invention (see FIG. 2), a thin layer of SiO₂ is used as an adhesion layer in a double-layer mask for defining the area of Josephson junctions. The SiO₂ adheres well to Nb (since it has also been optimized for an insulation layer), and also adheres very well to the top resist layer. Furthermore, SiO₂ is inert with respect to both aqueous and organic solvents used in anodization processing and resist processing (for both positive and negative resists), but can also be removed where necessary by standard etching techniques.

The invention recognizes that failure of interlayer adhesion between photoresist and Nb is a major cause of defects in the fabrication technology of the prior art. By substantially improving such adhesion, the present invention offers the possibility of improved reliability and IC yield.

In the prior art, the very same photoresist mask had to survive two subsequent fabrication steps—etching and self-aligned junction anodization (passivation) without loss of adhesion. The new technique is more robust in this respect since the bottom layer of the double-layer would prevent defect formation during anodization even if the top (resist) layer fails. This technique has been incorporated into a complete IC process, and indeed has resulted in substantially improved IC yield, especially for the smallest junctions (below 1.5 microns size) where the problems had previously been the most severe.

The present invention does increase the number of steps in the full process, since the SiO₂ layer in the mask must first be deposited, and subsequently etched away. (However, this etch-away step can be done simultaneously with the counter-electrode etching.) Nevertheless, this extra effort is easily worthwhile, since it enables the manufacturing (with reasonable yield) of higher-density superconducting ICs with greatly enhanced device speed and performance.

A second process improvement of the present invention replaces a wet-etch process for AlO_(x) removal in the prior art with an optimized dry-etch (or argon ion mill) process, in order to enhance junction uniformity and yield for small junctions.

A detailed description of a preferred embodiment of the invention, including a step-by-step process with fabrication parameters, is shown below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross section of a wafer having Nb/Al/AlO_(x)/Nb layers as used in the fabrication of superconducting devices such as a Josephson junction.

FIG. 2 shows a modification of the prior art process whereby dielectric layer of SiO₂ is deposited to act as an adhesion layer between the Nb and the photoresist layer deposited during the next process step.

FIG. 3 shows application of a photoresist layer on top of the silicon dioxide layer in accordance with one aspect of the invention.

FIG. 4 shows the photoresist area that defines the junction area after exposure and development of the photoresist.

FIG. 5 shows the etching of the SiO₂ adhesion layer and Nb counter-electrode down to the AlO_(x)/Al barrier layer.

FIG. 6A shows the results of a selective anodization step whereby all the exposed Al and part of the underlying Nb are converted to insulating oxides.

FIG. 6B shows a magnified view of the region inside the small dashed box in FIG. 6A.

FIG. 7 shows the removal of the photoresist layer.

FIG. 8 shows the result of coating and patterning of another photoresist layer designed to produce a protective anodization ring around the junction area.

FIG. 9 shows the etching (by Ar ion milling or dry reactive ion etching) of the anodized oxide (both AlO_(x) and NbO_(x) layers) except in the anodization ring (under the photoresist mask)

FIG. 10 shows the removal of the photoresist defining the anodization ring.

FIG. 11 shows the deposition of an SiO₂ insulating layer, designed to isolate the junction from subsequent wiring layers.

FIG. 12 shows the coating and patterning of a third photoresist layer, designed to produce a contact via to the Nb junction from a Nb wiring layer.

FIG. 13 shows the selective etching of the SiO₂ up to the Nb counter-electrode.

FIG. 14 shows the removal of the photoresist. Now the structure is ready for deposition of a Nb wiring layer

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A new fabrication method is proposed for increasing the yield and quality of superconducting junctions and more particularly Josephson junctions and Josephson-based digital and analog circuits in superconducting electronics. The method is based on using a double-layer mask for partial anodization of the junction side-walls and base-electrode around the junction. The top layer of this mask is a photoresist or electron-beam resist, and the bottom layer is a dielectric (e.g., SiO₂) that is insoluble in either aqueous or organic solvents. A more detailed description will now be given.

The existing fabrication scheme for making Nb-based Josephson tunnel junctions for superconducting electronics is comprised of the following fabrication steps:

1. As shown in FIG. 1, a Nb/Al/AlO_(x)/Nb trilayer is deposited in-situ on a wafer that includes or will include several other patterned layers of metal and dielectric. A tunnel barrier is formed by in-situ thermal oxidation of the Al layer in oxygen or an oxygen/argon mixture at a defined pressure, to form a thin (˜1-2 nm) layer of AlO_(x). Both the oxidation time and the pressure determine the properties of the tunnel barrier such as the Josephson critical current density J_(c). The bottom Nb layer is called the base electrode, and the top Nb layer is called the counter-electrode of the tunnel Josephson junctions.

2. FIG. 2 shows a step that differs from prior art fabrication techniques and will be discussed in more detail hereinafter.

3. The wafer is coated with either positive or negative resist (FIG. 3), and the resist etch mask is formed by optical or e-beam lithography (FIG. 4). The counter-electrode area is then defined by etching (FIG. 5), using e.g. plasma etching, reactive-ion etching, or high-density plasma etching. The AlO_(x)/Al layer acts as an etch stop. (Note—the prior art method does not include the thin SiO₂ layer shown in FIGS. 3, 4 and 5.)

4. After etching and without removing the resist, the wafer is immersed in an anodization solution, and all the surfaces that are not protected by the resist mask formed in step 5 are anodized. That is, the same resist etch mask is also used as an anodization mask. Anodization creates a bilayer of anodized Al (AlO_(x)) and anodized Nb (NbO_(x)) on the surface of the base electrode (FIG. 6). A layer of anodized Nb is also formed on all sidewalls of the junction's counter-electrode. This anodization step is very important because it encapsulates the junction's tunnel barrier with an anodized NbO_(x) layer, and this, protects it from reacting with water, oxygen, and other processing chemicals during all further wafer processing steps. This step also allows for opening a contact hole to the counter-electrode that is larger in size than the junction itself. The thickness of the anodized layer is controlled by the anodization voltage, usually in the range of 15-50 V. The initial anodization current density is in the range from 0.5-5 mA/cm².

5. After anodization, the resist is stripped (FIG. 7), and the wafer proceeds to the next fabrication steps that are intended to pattern the base electrode of the junction by lithography and etching. This may also require removing the anodization layer in some parts of the circuit. It remains around the junction (the anodization ring of FIGS. 8-10).

6. After base electrode patterning, the Josephson junction is completely formed. All other fabrication steps are necessary in order to interconnect junctions in the circuits (such as the SiO₂ insulating layer in FIGS. 11-14), and to create resistors for biasing and shunting the junctions. These steps may vary depending on the details the fabrication process.

One of the main sources of defects and loss of yield in this fabrication scheme is poor adhesion of the resist mask in step 3. Although this fact has not been recognized in the prior art. This may be due in part to the volume expansion of Nb and Al layers during anodization, which places significant local stresses on the photoresist mask. As a result, some parts of the resist mask may peel off during anodization, or anodization solutions may leach under the resist mask. This is especially a problem with many negative resists such as UVN®-30 (Shipley Company, Marlborough Mass.). Some photoresists may also be incompatible with (partially soluble in) the common anodization solutions. In these cases, some junctions may be degraded, or the counter-electrode of some junctions may be partially anodized, thus preventing a good (superconducting) electrical contact to be made to the junctions during the following fabrication steps.

One improvement of the invention is to use a double-layer anodization mask with the lower layer being an inorganic dielectric layer (such as SiO₂) that is insoluble in water, solvents, and components of the anodization solution, and the upper layer is the photoresist (or e-beam resist) layer. SiO₂ is especially suitable since it has already been optimized as an insulating layer in the prior-art Nb integrated circuit process, and is also fully compatible with standard Si-based resist processing. This double-layer mask is formed in the following simple way:

a. After the Josephson junction trilayer (Nb/Al/AlO_(x)/Nb) is formed as in step 1 above, a pinhole-free layer of SiO₂ is deposited by any appropriate method (e.g., rf magnetron sputtering, or plasma-enhanced chemical vapor deposition—PECVD) on top of the trilayer (see FIG. 2). The layer thickness may be anywhere from 5 to 300 nm, and is not critical, as long as it is free from pinholes. Thicker layers require long etch times, making them impractical.

b. A resist mask is formed in the same way as in step 4 above.

c. Then etching is done, using reactive ion etching (RIE) or inductively coupled plasma (ICP) with fluorine-based chemistry (e.g., SF₆, NF₃, or CF₄+O₂) such that both the SiO₂ overlayer and the Nb counter-electrode are etched in the same process. This may be a one-step process when the same etch parameters are used for both layers, or a two-step process when different etch recipes are used for etching first the SiO₂ and then the Nb counter-electrode. After completing the etch down to the AlO_(x)/Al layer in the trilayer structure (FIG. 5), the top of the Josephson junction will have a double-layer structure (Si0 ₂+resist) that serves as the double-layer anodization mask.

d. Etching is immediately followed by the anodization step 3, without removing the resist mask (FIG. 6). Now there is a layer of SiO₂ under the resist mask for extra protection.

The advantages of the proposed method are as follows. The SiO₂ layer improves the adhesion of the resist, and does not allow the anodization solution to leach underneath. Since the adhesion of sputtered or PECVD-deposited SiO₂ to Nb has already been optimized, and is stronger than the adhesion of the resist to Nb, the double-layer also protects the junction counter-electrode from being anodized even in the unlikely event that a part of the resist mask pops off, or if the anodization solution does leach under the resist. In the rare case that the SiO₂ layer has a pinhole or other defect, the presence of the resist on top still provides protection during the anodization. The probability that both layers of the double-layer anodization mask fail in the same location is much smaller than the probability of a failure of a single-layer resist mask. As a result, a dramatic increase in the yield and junction quality is achieved.

Another improvement over the prior art is described in reference to FIGS. 8 and 9, in defining the anodization ring around the Josephson junction. In the prior art, the AlO_(x) layer was first removed by a wet etch process, followed by reactive ion etching (RIE) for removing the NbO_(x) layer. However, a wet etch process can cause problems, that should preferably be avoided in high-reliability VLSI processing, particularly if sub-micron resolution is required. In the process of the present invention, this wet etch step is discarded, and two new approaches have been successfully demonstrated. In approach A, ion-milling with a neutral beam of argon (Ar) atoms is used to remove both the AlO_(x) and the NbO_(x) layers. In approach B, plasma etching (RIE or ICP) is used in a two-step process. First, a chlorine-based plasma is used to remove AlO_(x), and then a fluorine-based plasma is used to remove the NbO_(x). Either approach provides for increased yield and uniformity.

While various embodiments of the present invention have been illustrated herein in detail, it should be apparent that modifications and adaptations to those embodiments may occur to those skilled in the art without departing from the scope of the present invention as set forth in the following claims. 

What is claimed is:
 1. An integrated circuit based on a plurality of Nb-based Josephson junctions, comprising: a Josephson junction trilayer comprising a lower Nb-containing superconductive layer, an insulating layer, and an upper Nb-containing superconductive layer, on a substrate, fabricated into at least one Josephson junction having a defined junction area less than 1 square micron, the at least one Josephson junction comprising an anodized double oxide layer of AlOx on top of NbOx, wherein the double oxide is patterned in a vacuum processing chamber using a dry etch process to provide vertical sidewalls; and a silicon dioxide layer formed directly on top of the upper Nb-containing superconductor layer.
 2. The integrated circuit of claim 1, wherein the dry etch process comprises ion milling with a neutral beam of argon atoms.
 3. The integrated circuit of claim 1, wherein the dry etch process comprises the two sequential steps of: using a chlorine-based plasma etch to remove the top layer of AlOx; and using a fluorine-based plasma etch to remove the bottom layer of NbOx.
 4. The integrated circuit of claim 1, wherein the pattern definition comprises a layer of photoresist on top of the silicon dioxide, wherein the photoresist has a higher adhesion for the silicon dioxide than the upper Nb-containing superconductive layer.
 5. The integrated circuit of claim 1, wherein the Josephson junction trilayer comprises a sequence of Nb, Al, AlOx, and Nb, wherein the AlOx layer is between 1-2 nm thick.
 6. The integrated circuit of claim 1, wherein the at least one Josephson junction comprises at least one thousand Josephson junctions.
 7. The integrated circuit of claim 6, wherein the at least one thousand Josephson junctions each have operating superconducting critical currents that are within about 1% of a respective design specification.
 8. The integrated circuit of claim 6, wherein the integrated circuit comprises a plurality of functional circuits, each configured to operate at clock frequency of at least 100 GHz.
 9. The integrated circuit of claim 1, wherein the integrated circuit comprises at least one functional circuit configured to operate at clock frequency of at least 100 GHz.
 10. A Josephson junction integrated circuit, produced by a process comprising: depositing a Josephson junction trilayer comprising a lower superconductive layer, an insulating layer, and an upper superconductive layer, on a substrate; depositing a silicon dioxide layer directly on top of the upper superconductor layer by plasma-enhanced chemical vapor deposition (PECVD); depositing a photoresist having an adhesion to the silicon dioxide greater than a respective adhesion of the photoresist to the upper superconductive layer; patterning the photoresist; etching through the silicon dioxide layer and the upper superconductor layer to expose the insulating layer; anodizing exposed portions of the insulating layer and a portion of the lower superconductive layer; and dry etching the anodized insulating layer and the portion of the lower superconductive layer, to produce a device having vertical sidewalls.
 11. The Josephson junction circuit according to claim 10, further comprising removing the photoresist.
 12. The Josephson junction circuit according to claim 10, wherein the dry etching comprises ion-milling with a neutral beam of argon (Ar) atoms.
 13. The Josephson junction circuit according to claim 10, wherein the dry etching comprises plasma etching with a chlorine-based plasma and then a fluorine-based plasma.
 14. The Josephson junction circuit according to claim 13, wherein the dry etching comprises reactive ion etching.
 15. The Josephson junction circuit according to claim 13, wherein the dry etching comprises a inductively coupled plasma etching.
 16. The Josephson junction circuit according to claim 10, wherein the lower superconductive layer comprises niobium, the insulating layer comprises oxidized aluminum, and the upper superconductive layer comprises niobium.
 17. The Josephson junction circuit according to claim 10, wherein the silicon dioxide layer is formed by chemical vapor deposition with a layer thickness of between about 5-300 nm.
 18. A method of forming a Josephson junction integrated circuit, comprising: depositing a Josephson junction trilayer comprising a lower superconductive layer, an insulating layer, and an upper superconductive layer, on a substrate; depositing a silicon dioxide layer directly on top of the upper superconductor layer by plasma-enhanced chemical vapor deposition (PECVD); depositing a photoresist having an adhesion to the silicon dioxide greater than a respective adhesion of the photoresist to the upper superconductive layer; patterning the photoresist; etching through the silicon dioxide layer and the upper superconductor layer to expose the insulating layer; anodizing exposed portions of the insulating layer and a portion of the lower superconductive layer; and dry etching the anodized insulating layer and the portion of the lower superconductive layer, to produce a device having vertical sidewalls.
 19. The method according to claim 18, wherein the integrated circuit is patterned to define a plurality of interconnected Josephson junctions formed, further comprising operating the plurality of Josephson junctions at a clock rate of at least 100 GHz.
 20. The method according to claim 18, wherein the lower superconductive layer comprises niobium, the insulating layer comprises oxidized aluminum, and the upper superconductive layer comprises niobium; wherein the silicon dioxide layer is formed by chemical vapor deposition with a layer thickness of between about 5-300 nm; and wherein the dry etching comprises at least one of: ion-milling with a neutral beam of argon (Ar) atoms; inductively coupled plasma etching with a chlorine-based plasma and then a fluorine-based plasma; and reactive ion etching. 